AMD Unveils Next-Generation EPYC "Venice" Processor at CES 2026
At the 2026 International CES, AMD CEO Dr. Lisa Su introduced the highly anticipated EPYC "Venice" enterprise processor, a cornerstone of the company’s upcoming "Helios" AI rack systems. These advanced racks are designed to deliver exceptional performance for AI workloads, powered by the new AMD MI455X AI GPUs.
Revolutionary Architecture for AI and Enterprise Workloads
Each Helios rack node is equipped with four MI455X GPUs and a single EPYC "Venice" processor. The processor itself boasts an impressive 256-core, 512-thread configuration, setting a new standard for data center and AI infrastructure. The "Venice" chip introduces a significant architectural shift, featuring a redesigned chiplet layout compared to previous EPYC generations.
The processor package incorporates two slender, centralized server I/O dies (sIODs) manufactured on a cutting-edge 4 nm process. Flanking these I/O dies are up to eight Core Complex Dies (CCDs), each built on an advanced 2 nm node and housing 32 "Zen 6" cores. This innovative design aims to maximize compute density and efficiency for demanding enterprise applications.
Advanced Memory and Connectivity Features
The EPYC "Venice" processor supports a robust 16-channel DDR5 memory interface, providing 32 sub-channels for high bandwidth and low latency. This extensive memory support is likely a key reason for AMD’s decision to split the server I/O die into two interconnected chips, utilizing a high-speed switching fabric for seamless communication.
In addition to memory enhancements, "Venice" is expected to offer a substantial increase in PCIe and CXL lane counts compared to current-generation EPYC processors. This expansion is designed to accommodate the four MI455X AI GPUs per node, as well as support for Data Processing Units (DPUs) and 800G network interface cards (NICs), ensuring the platform is ready for the most demanding AI and data center workloads.
Unanswered Questions and Future Potential
While AMD has not yet confirmed whether the "Venice" processor utilizes full-sized "Zen 6" cores capable of sustaining high clock speeds or more compact "Zen 6c" cores optimized for efficiency, both options promise identical instruction set architecture (ISA) and instructions per cycle (IPC). This flexibility could allow AMD to tailor performance and power efficiency to specific enterprise needs.
With the introduction of the EPYC "Venice" processor and the Helios AI rack, AMD is poised to redefine performance standards in the enterprise and AI computing landscape. The combination of advanced chiplet design, expanded memory bandwidth, and increased connectivity positions AMD as a leader in next-generation data center solutions.
