Intel Desktop Platform Refresh

Intel is gearing up for a major update to its desktop platform this year, with the upcoming release of the Core Ultra 200 series processors based on the "Arrow Lake" microarchitecture. The company decided to skip a desktop processor based on "Meteor Lake" due to performance limitations, leading to the development of the 14th Gen Core "Raptor Lake Refresh" generation to bridge the gap until 2024. The new "Arrow Lake-S" Core Ultra 200 series is expected to launch in late Q3 or early Q4 of 2024, with the initial release featuring overclocker-friendly K- and KF SKUs and motherboards based on the Intel Z890 chipset. In 2025, more affordable processor models and mainstream chipsets like the B860 will be introduced, requiring a new motherboard with the Socket LGA1851.

Recent leaks from Jaykihn have revealed core configurations of the "Arrow Lake-S" chip, confirming 8 P-cores and 16 E-cores in its maximum setup. The P-cores are "Lion Cove" with 3 MB of L2 cache each, while the E-cores are "Skymont" arranged in 4-core modules sharing 4 MB L2 caches. Intel claims a 14% IPC increase for the "Lion Cove" P-cores over the previous generation, relying on the "Skymont" E-cores for improved multithreaded performance. The Core Ultra 9 series will feature an 8P+16E configuration, while the Core Ultra 7 series will have 8P+12E.

The Core Ultra 5 series will be split into two categories, with the K SKU based on B0 silicon and featuring a 6P+8E configuration, and other SKUs based on C0 silicon with a maximum of 6 P-cores and 8 E-cores. The iGPU for the "Arrow Lake-S" processor will have 4 Xe cores based on the Xe2 "Battlemage" architecture, providing ample performance for non-gaming setups with high-resolution monitors.

The Core Ultra 9 series is expected to have the iGPU enabled with all 4 Xe cores, while the Core Ultra 7 series will offer K and KF SKUs with varying iGPU configurations. The Core Ultra 5 K-series SKU will have the maxed out iGPU, while the non-K/KF SKUs will have different iGPU configurations based on the C0 silicon.